Field of the Invention
The invention relates to a circuit configuration for controlling write operations and read operations in a magnetoresistive memory configuration.
In magnetoresistive memories (MRAMs), the memory effect is a result of the magnetically variable electrical resistance of the memory cell. Such a memory cell is disposed at the crossover between a bit line and a word line, which are provided orthogonally with respect to one another. At the crossover point between these conductors there is a specific multilayer system formed of a stack of a soft-magnetic material and a hard-magnetic material one above the other, between which there is a tunnel oxide. The value of the resistance contained in the memory cell between the conductors WL and BL depends on whether the magnetization direction in the materials is parallel (low cell resistance) or antiparallel (high cell resistance). The cell is written to by switching the soft-magnetic film through an electromagnetic field. The switching process requires a superposition of the two magnetic fields of a word line and a bit line. In order that the soft-magnetic layer can be polarized in two opposite directions, it is necessary that at least one of the programming currents can flow in both directions through the corresponding lines.
Thus, in order to generate the writing magnetic field, an impressed current is required on the corresponding lines (word line and bit line), wherein the current flows in both directions on the bit line irrespective of whether it is desired to write a logic xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d. For performing a read operation, a specific voltage is applied to the cell to be read and the current flowing through the cell is measured.
It is accordingly an object of the invention to provide a circuit configuration which is suitable for controlling write and read operations in an MRAM memory configuration of this type, i.e. a selection circuit on the bit lines, which can fulfil the above-described functions for writing and reading a logic 1 or a logic 0 to and from the respective memory cells. A further object is to provide an MRAM memory configuration which is equipped with a selection circuit of this type.
With the foregoing and other objects in view there is provided, in accordance with the invention, in an MRAM memory configuration having a plurality of magnetoresistive memory cells with associated bit lines and word lines respectively running in a row direction and a column direction and crossing one another at respective ones of the magnetoresistive memory cells, a circuit configuration for controlling write operations and read operations, including:
column select lines for providing column select signals;
selection transistors connected to the bit lines, the selection transistors having respective control electrodes connected to the column select lines and being controllable via the column select signals;
given ones of the selection transistors being first selection transistors, each of the bit lines having ends and having a respective one of the first selection transistors provided at the ends of each of the bit lines on both sides of each of the magnetoresistive memory cells;
read/write amplifiers having respective current sources and current sinks;
output lines connected to the read/write amplifiers;
the first selection transistors being grouped in sections including equal numbers of the first selection transistors, the first selection transistors of each of the sections being jointly connected, at the ends of the bit lines, to a respective interacting pair of the read/write amplifiers via those electrode terminals of the first selection transistors that are not connected to the bit lines; and
the read/write amplifiers being controlled such that if a write signal is fed thereto, write currents for writing one of a logic xe2x80x9c1xe2x80x9d and a logic xe2x80x9c0xe2x80x9d flow selectively in a first direction and in a second direction opposite thereto in all of the bit lines selected by a corresponding column select signal on a respective one of the column select lines and, if a read signal is fed in, a logic state stored in a selected one of the magnetoresistive memory cells can be read out via a given one of the output lines.
In other words, a circuit configuration for controlling write and read operations in an MRAM memory configuration, which has a plurality of magnetoresistive memory cells with associated bit lines and word lines which run in the row and column directions and cross one another at the respective memory cell, wherein selection transistors are connected to all of the bit lines, the control electrodes of which transistors can be driven by column select signals fed via column select lines, wherein each bit line in each case has a first selection transistor at its ends on both sides of each memory cell, the first selection transistors, which are combined in sections in the same number in each case, at each end of the bit lines, are jointly connected to a respective interacting read/write amplifier pair by their electrode terminals that are not connected to the bit line, each read/write amplifier of which pairs has a current source and a current sink and is connected in such a way that, through a write signal that drives them, in all bit lines selected by a corresponding column select signal on the respective column select line write currents for writing a logic xe2x80x9c1xe2x80x9d or a logic xe2x80x9c0xe2x80x9d selectively flow in a first direction or in a second direction opposite thereto and, in the event of a read signal being fed in, a logic state stored in the selected memory cell can be read out via an output line.
In accordance with one essential aspect of the invention there is a circuit configuration for controlling write and read operations in an MRAM memory configuration, which has a plurality of magnetoresistive memory cells with associated bit and word lines which run in the row and column directions and cross one another at the respective memory cell, selection transistors being connected to all of the bit lines, the control electrodes of which transistors can be driven by column select signals fed via column select lines. Each bit line in each case has a first selection transistor at its two ends. The first selection transistors, which are combined in sections in the same number in each case, at each end of the bit lines, are jointly connected to a respective interacting read/write amplifier pair by their electrode terminals that are not connected to the bit line, each read/write amplifier of which pairs has a current source and a current sink and is connected in such a way that, through a write signal that drives them, in all bit lines selected by a corresponding column select signal on the respective column select line write currents for writing a logic xe2x80x9c1xe2x80x9d , or a logic xe2x80x9c0xe2x80x9d optionally flow in a first direction or in a second direction opposite thereto and, in the event of a read signal being fed in, a logic state stored in the selected memory cell can be read out via an output line of the read/write amplifiers.
In order that the non-selected bit lines are kept at a specific potential, second selection transistors are connected to the two ends of the bit lines, the control electrodes of which transistors are driven by the complement of the respective column select signal and a constant voltage is jointly applied to those electrode terminals of the transistors which are not connected to the bit lines.
In principle, there are two different possible forms of organization of the bit lines of an MRAM memory array:
1) the bit block configuration and
2) the word block configuration, which is similar to the word block configuration that is selected in the case of DRAMs.
If the bit lines are formed as bit blocks, the first selection transistors at the two ends of in each case n successive bit lines of the bits of the memory configuration that are assigned in each case to one of a plurality of bit blocks are in each case jointly connected to the interacting read/write amplifier pair and a respective column select line selects, through the associated first selection transistor, one of the n bit lines of each bit block, the constant voltage being jointly applied to the second selection transistors of the bit blocks likewise block by block at the two ends of the bit lines.
One bit block may include for example n=4 bit lines.
The constant voltage is preferably fed to the second selection transistors from both sides of the bit lines.
If the bit lines or the memory cell array are subdivided into block sections word block by word block, the bits of a word of the MRAM memory configuration are physically provided next to one another, in which case a respective column select line, through the use of the column select signal fed in, in each case selects one word block from m word blocks, the word block including n bits and corresponding n bit lines, and connects these n bit lines to associated n multiplexed bit lines, the first selection transistors in each case one of the n bit lines of all m word blocks and a respective read/write amplifier pair being connected to the multiplexed bit lines.
In the word block configuration, the constant voltage is preferably also applied to the second selection transistors word block by word block. This constant voltage is preferably fed to the bit lines from both sides.
According to another feature of the invention, given ones of the selection transistors are second selection transistors respectively connected to the two ends of each of the bit lines; and the control electrodes of the second selection transistors are driven by a complement of the corresponding column select signal and a constant voltage is jointly applied to those electrode terminals of the second selection transistors that are not connected to the bit lines such that the bit lines which are not selected by a column select signal are kept at a given potential.
According to another feature of the invention, the MRAM memory configuration is organized in bit blocks such that the first selection transistors of in each case n successive ones of the bit lines associated with bits of the MRAM memory configuration that are assigned in each case to one of the bit blocks are, at the two ends of the successive ones of the bit lines, in each case jointly connected to an interacting pair of the read/write amplifiers, with n being an integer number; a respective one of the column select lines selects one of the n successive ones of the bit lines from each of the bit blocks; and given ones of the selection transistors are second selection transistors respectively connected to the two ends of each of the bit lines, and given ones of the second selection transistors associated with the one of the bit blocks are in each case jointly supplied with a constant voltage at the two ends of the bit lines.
According to yet another feature of the invention, the MRAM memory configuration is organized in word blocks such that all bits of a word of the MRAM memory configuration are physically provided next to one another, a respective one of the column select lines selects, with a column select signal, one of the word blocks from m of the word blocks, the one of the word blocks is formed of n bits and corresponding n bit lines, and the respective one of the column select lines switches the n bit lines to associated n multiplexed bit lines, with n and m being integer numbers; and the first selection transistors on both sides of in each case one of the n bit lines of all m word blocks and a respective interacting pair of the read/write amplifiers are connected to the n multiplexed bit lines.
According to a further feature of the invention, the MRAM memory configuration is configured such that a quotient m:4 is a power of 2, with m being an integer number.
A magnetoresistive memory configuration according to the invention is distinguished by the fact that it has such a circuit configuration described above for controlling the write and read operations.
The description below describes, with reference to the accompanying drawing, two basic embodimentsxe2x80x94which differ with regard to their form of organizationxe2x80x94of the circuit configuration according to the invention, in each case with a magnetoresistive memory configuration equipped with the circuit configuration according to the invention.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a circuit configuration for controlling write and read operations in a magnetoresistive memory configuration, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.